rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad8026 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 quad high speed amplifier functional block diagram r f r g r g r f v ee v cc ad8026 r f r p r p out a Cin a +in a +in b Cin b out b out d Cin d +in d +in c Cin c out c r f r g r p r p r g product description the ad8026 is a complete low cost, closed loop, voltage feed- back, quad amplifier. precision trimmed resistors set a fixed r f / r g ratio of 5/3 to a typical gain accuracy of 0.02%. manufac- tured on adis proprie tary xfcb high speed bipolar process, which enables the ou tput drivers to settle to within 0.1% within 55 ns into a 100 pf load (4 v swing) and drive output voltages to rated settling time to within 0.5 v from the rail. the typical 3 db bandwidth is 60 mhz, at g = +2.67. the ad8026 is laser trimmed to produce both exceptional offset and gain perfor mance. the low settling time, high slew rate, low offset and rail-to-rail output voltage drive capability makes the ad8026 ideal for driving lcd displays. the ad8026 is available in a 14-lead soic package. features voltage feedback, rail-to-rail output rated settling time to within 0.5 v of supply rail quad high speed amplifier settling time to 0.1% of 55 ns (4 v swing, c l = 100 pf) slew rate 135 v/ m s (4 v swing) C3 db bandwidth 60 mhz fixed gain resistors for high dc accuracy low voltage offset 0.5 mv rto typical gain error less than 0.05% low supply current 3.4 ma nominal +12 v supply 14-lead soic package applications lcd source drivers cd dvd cdr 1v/div 1v/div 50ns/div input output v out = 4v v in = 1.5v r l = 10k v figure 1. 4 v step response
C2C rev. 0 ad8026Cspecifications parameter conditions min typ max units dynamic performance C3 db small signal bandwidth v in = 50 mv rms r l = 1 k w 20 60 mhz bandwidth for 0.1 db flatness v in = 50 mv rms r l = 1 k w 12 mhz slew rate v o = 4 v step 135 v/ m s full power response v o = 2 v p-p 10 mhz settling time to 0.1% v o = 4 v step, c l = 100 pf, r s = 50 w 55 ns noise/distortion performance total harmonic distortion f c = 5 mhz, v o = 2 v p-p, r l = 1 k w C60 dbc voltage noise (rto) 1 f = 10 khz 67 nv/ ? hz crosstalk, output to output f = 5 mhz, v o = 2 v p-p, r l = 1 k w C80 db differential gain error ntsc r l = 1 k w 0.02 % differential phase error ntsc r l = 1 k w 0.02 degrees dc performance rto offset voltage 2 v in = 0 v 0.5 5.5 mv t min to t max 6mv rto offset drift 10 m v/ c +input bias current 0.6 1.6 m a closed-loop gain error 3 r l = 10 k w , C2.67 < v o < +2.67 C0.02 0.05 % t min to t max 0.05 % gain matching channel-to-channel, r l = 10 k w 0.03 % input characteristics +input resistance 170 k w +input capacitance 2.5 pf output characteristics output voltage swing r l = 10 k w , v cc C v oh , v ee + v ol 0.2 0.25 v short circuit output current 175 ma power supply operating range 4 13 v quiescent current/amp 3.2 3.4 ma/amp power supply rejection ratio (rto) +v s = 5.5 v to 6.5 v, Cv s = C6 v 48 60 db Cv s = C5.5 v to C6.5 v, +v s = 6 v 48 65 db operating temperature range 0 +70 c notes 1 includes gain resistor thermal noise. 2 rto offset includes effects of input voltage offset, input current, and input offset current. 3 measured in the inverting mode. 4 observe absolute maximum ratings. specifications subject to change without notice. (@ +25 8 c, v s = 6 6 v, r i = 500 v , r l = 10 k v , r f = 5k, r g = 3k noninverting configuration, t min = 0 8 c, t max = +70 8 c, unless otherwise noted.)
ad8026 C3C rev. 0 absolute maximum ratings 1 supply voltage v cc Cv ee . . . . . . . . . . . . . . . . . . . . . . . 14.0 v internal power dissipation 2 small outline package (r) . . . . . . . . . . . . . . . . . . . . 0.9 w +input voltage v cc Cv in + . . . . . . . . . . . . . . . . . . . . . . < 12 v Cinput voltage . . . . . . . . . . . . . . . . . . . . . . . . . . < v ee + 12 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > v ee C 12 v output short circuit duration . . . . . . . . . . . . . . . . . . . . observe power derating curves storage temperature range . . . . . . . . . . . . C65 c to +125 c operating temperature range (a grade) . . . . 0 c to +70 c lead temperature range (soldering 10 sec) . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device in free air: 14-lead soic package: q ja = 120 c/w, where p d = (t j C t a )/ q ja . maximum power dissipation the maximum power that can be safely dissipated by the ad8026 is limited by the associated rise in junction tempera- ture. the maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition tem- perature of the plastic, approximately +150 c. exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of +175 c for an extended period can result in device failure. while the ad8026 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (+150 c) is not exceeded under all conditions. to ensure proper operation, it is necessary to observe the maximum power derating curves. ambient temperature C 8 c 1.5 1.0 0.5 C10 80 0 maximum power dissipation C watts 10 20 30 40 50 60 70 t j = +150 8 c figure 2. maximum power dissipation vs. temperature ordering guide temperature package package model range description option ad8026ar 0 c to +70 c 14-lead plastic soic so-14 AD8026AR-REEL 0 c to +70 c reel soic so-14 AD8026AR-REEL7 0 c to +70 c reel 7 soic so-14 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8026 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device pin configuration top view (not to scale) 14 13 12 11 10 9 8 1 2 3 4 5 6 7 Cin a +in a v cc +in b Cin b out b out d Cin d +in d v ee +in c out a ad8026 Cin c out c
ad8026Ctypical performance characteristics C4C rev. 0 frequency C hz 0.5 0.4 C0.5 0.1 C0.2 C0.3 C0.4 0.3 0.2 C0.1 0 100k 500m 1m 10m 100m normalized flatness C db C8 normalized output C db 2 1 0 C1 C2 C3 C4 C5 C6 C7 v in = 50mv rms r l = 1k v r s = 0 v c l = 0pf figure 3. small signal bandwidth and 0.1 db flatness 20mv/div 25mv/div 50ns/div v out = 100mv v in = 37.5mv r l = 10k v figure 4. 100 mv step response 0.1%/div time C ns 0 20 40 60 80 100 120 140 160 180 v in = 4v step r l = 10k v r s = 50 v c l = 100pf figure 5. short-term settling time frequency C hz 100k 500m 1m 10m 100m output C dbm v in = 2.0v p-p r l = 1k v C8.5 C5.5 C2.5 0.5 3.5 6.5 9.5 12.5 15.5 18.5 21.5 v in = 1.0v p-p v in = 0.5v p-p v in = 0.25v p-p figure 6. large signal bandwidth frequency C hz 100k 500m 1m 10m 100m c l = 100pf c l = 200pf c l = 300pf v in = 50mv rms r l = 1k v r s = 25 v normalized output C db 3 2 1 0 C1 C2 C3 C4 C5 C6 C7 figure 7. cap load vs. frequency frequency C hz 0 C20 C120 100k 100m 1m 10m C40 C60 C80 C100 v out = 2v p-p r l = 1k v crosstalk C db figure 8. crosstalk (output-to-output) vs. frequency
ad8026 C5C rev. 0 ire 12 3 45678 91011 diff phase C degrees ntsc 0.02 0.01 0.00 C0.02 C0.01 0.03 C0.03 diff gain C % ntsc ire 12 3 45678 91011 0.02 0.01 0.00 C0.02 C0.01 0.03 C0.03 figure 9. differential gain and differential phase 0 C0.2 C1.8 v os rto C mv C1.0 C1.2 C1.4 C1.6 C0.6 C0.8 C0.4 temperature C 8 c 15 25 40 55 70 0 C15 figure 10. v os rto vs. temperature 0 C0.0005 C0.0025 gain accuracy C % C0.0015 C0.002 C0.001 temperature C 8 c 15 25 40 55 70 0 figure 11. gain accuracy vs. temperature 10 100 noise voltage, rto C nv/ hz noise current C pa/ hz frequency C hz 10000 10k 100k 1000 100 10 1k 100 10 1 0.1 e n i n figure 12. noise (rto) vs. frequency frequency C hz C30 C90 C130 1m 10m distortion C dbc C100 C110 C120 100k C40 C50 C60 C70 C80 r l = 1k v v out = 2v p-p figure 13. total harmonic distortion frequency C hz 20 10 C80 30k 100m 100k 1m 10m C20 C50 C60 C70 0 C10 C40 C30 power supply rejection ratio C db Cpsrr +psrr figure 14. psrr vs. frequency
ad8026 C6C rev. 0 frequency C hz 100 10k 100m 100k 1m 10m 0.1 0.01 10 1 output impedance C v 1g figure 15. output impedance vs. frequency frequency C hz 1m 10k 100m 100k 1m 10m 1k 100 10k input impedance C v 1g 100k 10 figure 16. input impedance vs. frequency frequency C hz 20 C10 C20 10 0 normalized output C db 1 0 v 24.9 v 49.9 v 100 v r s 3k v 1875 v + C c l 5k v v in = 50mv rms c l = 100pf 100k 1m 10m 100m 500m figure 17. bandwidth and flatness vs. series resistance into 100 pf theory of operation the ad8026, a quad voltage feedback amplifier with rail-to-rail output swing, is internally configured for a gain of either C5/3 or +8/3. the gain-setting resistors are laser trimmed for precise control of their ratio. in addition, the amplifiers frequency response has been adjusted to compensate for the parasitic capacitances associated with the gain resistors and with the amplifiers inverting input. the result is an amplifier with very tight control of closed-loop gain and settling time. the amplifiers input stage will operate with voltages from about C0.2 v below the negative supply voltage to within about 1 v of the positive supply. exceeding these values will not cause phase reversal at the output; however, the input esd protection de- vices will begin to conduct if the input voltages exceed the sup- ply rails by greater than 0.5 v. the gain resistors that connect to pins 2, 6, 9, and 13 are protected from esd in such a way that the voltages applied to these pins may exceed the negative sup- ply by as much as C7 v. the rail-to-rail output range of the ad8026 is provided by a complementary common-emitter output stage. the chosen circuit topology allows the outputs to source and sink 50 ma of output current and, with the use of an external series resistor, to achieve rapid settling time while driving capacitive loads within 0.5 v of the supply rails. output referred offset voltage the output referred offset voltage for a voltage feedback ampli- fier can be estimated with the following equation: v oos = v ios 1 + r f / r g () + i os r f i r g () + i b r p - r f i r g () () where: v oos = output referred offset voltage, v ios = input referred offset voltage, i os = difference of the two input currents, i b = average of the two input currents, r p = total resistance in series with positive input, r f = 5 k w , r g = 3 k w for this part. this equation leads to the well known conclusion that, for a voltage feedback amplifier to maintain minimum output offset voltage, the value of r p should be selected to match the parallel combination of r f and r g . it should be noted that the ad8026 was designed for an assumed source impedance, of 500 w driv- ing the +input. therefore, the value of r p included on the chip is 500 w less than the ideal value for minimum output offset. additional resistance may be added externally, in series with the +input, if the part is to be driven by a lower impedance source. applications the ad8026 is designed with on-chip resistors for each op amp to provide accurate fixed gain and low output-referenced offset voltages. this can result in significant cost and board-space savings for systems that can take advantage of the ad8026 specifications. the part is actually trimmed in three steps. first, the supply current of the part is trimmed. then the gain is accurately trimmed to specification. this trim adjusts the values of either the gain or feedback resistor for a ratio of 5 to 3. the final trim is for the offset voltage. for this trim, the Cinput is connected to ground and the +input is connected to ground via 500 w , while internal offset resistors are trimmed.
ad8026 C7C rev. 0 in a system application, the part is designed assuming that each Cinput will be driven from a low impedance source, while each +input will be driven by a current-output dac with a 500 w termination resistor. thus, to first order, each on-chip series input resistor to each +input is 500 w less than the parallel combination of the gain-setting resistors. the offset-inducing effect of the bias currents is minimized by this scheme. figure 18 shows how to drive the ad8026 with a fixed positive gain of 8/3 from a current output dac. the gain and offset errors are minimized by using a 500 w resistor (r i ) to convert the dac output current into a voltage. the gain resistor (r g ) should be directly connected to ground, or driven from a low output impedance source to ensure minimum offset and maxi- mum gain accuracy. if the +input of any of the op amps is driven from a voltage source, the low offset voltage of the ad8026 can be maintained by adding a series resistance of 500 w between the source and the +input to the ad8026. this is illustrated in figure 19. if the Cinput is to be driven, such as when creating an offset volt- age, then a low source impedance should be provided in order to maintain both gain and offset accuracy. +i b Ci b r p 1/4 ad8026 r f r g r i 500 v v in current- output dac v out Cv s 10 m f 0.1 m f +v s r s c l 10 m f 0.1 m f figure 18. low offset and high gain accuracy circuit for driving the ad8026 from a current output dac voltage- output driver +i b Ci b r p 1/4 ad8026 r f r g r i 500 v v in v out Cv s 10 m f 0.1 m f +v s r s c l 10 m f 0.1 m f figure 19. low offset and high gain accuracy circuit for driving the ad8026 from a voltage source quad amplifier characterization board figure 20. component side figure 21. solder side figure 22. silkscreen
ad8026 C8C rev. 0 c3327C8C4/98 printed in u.s.a. 14-lead soic (so-14) 14 8 7 1 0.3444 (8.75) 0.3367 (8.55) 0.2440 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (3.80) pin 1 seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) bsc
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